EXTS=0, BEM=0, SWSEN=0, ASET=00, WRAH=00, RDAH=00, BLS=0, BSTW=0, BSTR=0, AA=0, PS=00
Chip Select Control Register
| BSTW | Burst-Write Enable 0 (0): Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 1 (1): Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. |
| BSTR | Burst-Read Enable 0 (0): Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 1 (1): Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. |
| BEM | Byte-Enable Mode 0 (0): FB_BE is asserted for data write only. 1 (1): FB_BE is asserted for data read and write accesses. |
| PS | Port Size 0 (00): 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 1 (01): 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. |
| AA | Auto-Acknowledge Enable 0 (0): Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 1 (1): Enabled. Internal transfer acknowledge is asserted as specified by WS. |
| BLS | Byte-Lane Shift 0 (0): Not shifted. Data is left-aligned on FB_AD. 1 (1): Shifted. Data is right-aligned on FB_AD. |
| WS | Wait States |
| WRAH | Write Address Hold or Deselect 0 (00): 1 cycle (default for all but FB_CS0 ) 1 (01): 2 cycles 2 (10): 3 cycles 3 (11): 4 cycles (default for FB_CS0 ) |
| RDAH | Read Address Hold or Deselect 0 (00): When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 1 (01): When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 2 (10): When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 3 (11): When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. |
| ASET | Address Setup 0 (00): Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 1 (01): Assert FB_CSn on the second rising clock edge after the address is asserted. 2 (10): Assert FB_CSn on the third rising clock edge after the address is asserted. 3 (11): Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ). |
| EXTS | Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted. 0 (0): Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 1 (1): Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. |
| SWSEN | Secondary Wait State Enable 0 (0): Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 1 (1): Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. |
| SWS | Secondary Wait States |